Exemplary embodiments of the present invention relate to a semiconductor device and a fabrication method thereof, and more particularly, to a semiconductor device including an isolation layer, and a method for forming an isolation layer of a semiconductor device.
A semiconductor device includes an isolation layer for isolating devices one from another. As semiconductor devices become highly integrated, a conventional LOCal Oxidation of Silicon (LOCOS) process for forming an isolation layer is reaching its limits. Therefore a method of forming an isolation layer using a shallow trench isolation (STI) process is being used instead.
Hereafter, a conventional method of forming an isolation layer of a semiconductor device will be described with reference to the accompanying drawings.
FIGS. 1A to 1D are cross-sectional views illustrating a conventional method of forming an isolation layer of a semiconductor device. Referring to FIG. 1A, a substrate 10 including a cell region CELL and a peripheral region PERI is provided. The peripheral region includes a PMOS region, where a PMOS transistor is to be formed, and an NMOS region, where an NMOS transistor is to be formed.
Subsequently, after a pad oxide layer 11 and a pad nitride layer 12 are sequentially formed over the substrate 10, the pad nitride layer 12 and the pad oxide layer 11 are etched, and the substrate 10 is etched to a predetermined depth to form a plurality of trenches for device isolation.
Subsequently, an oxidation process is performed to cure the damage on the substrate caused during the etch process for forming the trenches for device isolation. Through the oxidation process, a sidewall oxide layer 13 is formed on the surface of the substrate 10 exposed on the internal wall and the bottom of the plurality of the trenches for device isolation.
Subsequently, a liner nitride layer 14 and a liner oxide layer 15 are sequentially formed over the substrate 10 with the sidewall oxide layer 13 formed therein. The liner nitride layer 14 and the liner oxide layer 15 are simultaneously formed in the cell region and the peripheral region. In particular, since the liner nitride layer 14 and the liner oxide layer 15 are formed over the trenches for device isolation of the cell region and the peripheral region, isolation layers disposed in the cell region and the peripheral region include the liner nitride layer 14 and the liner oxide layer 15.
With the liner oxide layer 15 formed, a first insulation layer may be deposited in a subsequent process with increased efficiency. Also, with the liner nitride layer 14, it is possible to reduce the stress applied to the substrate 10 and prevent impurities of an isolation layer from being diffused into the substrate 10 in a subsequent thermal treatment. Therefore, the refresh characteristics of a semiconductor device can be improved.
In case of the liner nitride layer 14 formed in the PMOS region, however, hot electrons are trapped to induce attraction to holes. Therefore, holes are accumulated on the internal wall of the trenches for device isolation to decrease the width of a channel, and accordingly, a hot electron-induced punch through (HEIP) phenomenon is caused. As a result, current leaks out of a source/drain of a PMOS transistor.
Therefore, a process for selectively removing the liner nitride layer 14 formed over the PMOS region is subsequently performed.
Referring to FIG. 1B, a photoresist is applied to the substrate 10 with the liner nitride layer 14 and the liner oxide layer 15 formed therein. A photoresist pattern 16 is formed to open the PMOS region, while covering the cell region and the NMOS region through an exposure and development process.
Subsequently, the liner oxide layer 15, exposed in the PMOS region, is removed using the photoresist pattern 16 as an etch barrier. As a result, the liner nitride layer 14 the PMOS region is exposed.
Referring to FIG. 1C, after the photoresist pattern 16 is removed, the liner nitride layer 14 of the PMOS region is removed using the liner oxide layer 15 of an NMOS region as an etch barrier. Through this process, the liner nitride layer 14 of the PMOS region may be selectively removed.
Referring to FIG. 1D, an insulation layer 17 is formed over the resultant structure and a planarization process is performed until a surface of the pad nitride layer 12 is exposed. As a result, a plurality of isolation layers including the insulation layer 17 in the cell region and the peripheral region are formed.
Subsequently, the pad nitride layer 12 and the pad oxide layer 11 are removed, and a surface of the substrate 10 is exposed to thereby complete the formation of an STI structure. The liner oxide layer, the liner nitride layer and the insulation layer 17 may be partly removed in the course of removing the pad nitride layer 12 and the pad oxide layer 11. Referring to FIG. 1D, the liner oxide layer a portion of which is removed is denoted with a reference numeral ‘15A,’ and the liner nitride layer a portion of which is removed is denoted with a reference numeral ‘14A.’
However, according to the conventional technology described above, since the liner nitride layer 14 is formed both in the cell region and the peripheral region, a few problems occur in the course of removing the liner nitride layer 14 of the PMOS region.
First, it is not easy to coat and remove a photoresist. As described before with reference to FIG. 1B, the substrate with the trenches for device isolation for forming the photoresist pattern 16 opening the PMOS region is coated with the photoresist. Since the photoresist is applied to the intermediate structure with a step in height, the photoresist may not be applied smoothly, and the adhesion of the photoresist may be low. Also, when the photoresist is removed, it may not be completely removed due to the step in height and thus residues may remain.
Second, the above described fabrication process is complicated, and its manufacturing costs are rather high. As described before with reference to FIG. 1C, after the liner oxide layer 15 is removed, the photoresist pattern 16 should be removed. The photoresist removing process is generally performed through a photoresist (PR) strip process. Also, the liner nitride layer 14 is removed through a wet dip-out process using phosphate. In short, the conventional technology raises concerns that the fabrication process is rather complicated because the liner nitride layer 14 formed in the PMOS region is selectively removed and the manufacturing costs are high.